Failure-Erasure Circuitry: A Duplicative Technique of Failure-Masking Systems

There are generally considered to be four major types of digital circuit redundancy techniques in use today. They are the Shannon-Moore component redundancy method, the "quadded logic" approach suggested by Tryon,von Neumann's triplication and majority-voting technique, and the basic standby redundancy systems. When viewed in the light of design criteria which are based upon the requirements of non-maintainable spacecraft, it appears that the triplication and majority-voting scheme is optimal, although more costly in weight, power, and component cost than one would prefer. It is the purpose of this paper to describe a redundancy technique which would require mere duplication to achieve the same failure-masking capabilities as the von Neumann method. An analysis of the circuit-failure problem is approached from the viewpoint of coding theory with comparisons made between the "noisy channel" and "circuit-failure" problems. Some of the difficulties of extrapolating from the former to the latter are discussed, as well as recent attempts to minimize the redundancy "overhead" by coding over larger numbers of bits. Following a description of the binary erasure channel model, a proposal of a failure-erasure technique based upon it is outlined. The method enables failure-masking at duplicative rather than triplicative costs. There are constraints which this scheme imposes upon the circuit elements, however, and the characteristics of the ideal circuit element and logic signaling are proposed. The paper concludes with a discussion of existing hardware which approximates the desired characteristics. Accepted for the Air Force Stanley J. Wisniewski Lt Colonel, USAF Chief, Lincoln Laboratory Office